The present invention generally relates to semiconductor devices and more particularly to a compound semiconductor device operating in an enhancement-mode.
Compound semiconductor devices have an advantageous feature of high operational speed due to the small effective mass of electrons. Further, in view of low operational voltage, compound semiconductor devices are used extensively in electronic apparatuses for use in ultra-high frequency applications including mobile telephones and portable telephones. Conventionally, depletion-mode compound semiconductor devices have been used successfully in such ultra-high frequency applications for the final stage power transistor.
On the other hand, the use of such a depletion-mode power transistor has caused the problem that a negative voltage source has to be provided in the electronic apparatus in addition to a positive voltage source for driving the depletion-mode power transistor. In relation to the use of the additional voltage source, it has been difficult, in conventional electronic apparatuses having a depletion-mode compound semiconductor device as a power transistor, to reduce the size and cost or power consumption.
Meanwhile, compound semiconductor devices of the enhancement-mode have an advantageous feature in that the negative voltage source is not necessary. Thereby, the enhancement-mode compound semiconductor devices are promising devices for reducing the size and cost or power consumption of the electronic apparatus.
When using an enhancement-mode compound semiconductor device in such ultra-high frequency applications, it is desired to reduce the leakage current in the turn-off state thereof and increase the current density in the turn-on state as much as possible, so that high output power and high efficiency are achieved.
In an enhancement-mode power FET, on the other hand, the turn-off state leakage current and the turn-on state current density are generally in a trade-off relationship, and it has been difficult to increase the turn-on state current density and simultaneously minimize the turn-off state leakage current.
FIG. 1 shows the construction of a typical enhancement-mode MESFET 10 having a diffusion region.
Referring to FIG. 1, the MESFET 10 is formed on a semi-insulating GaAs substrate 11 and includes a GaAs channel layer 12 of the n-type formed on the substrate 11, wherein a gate electrode 13A is formed on the channel layer 12 in correspondence to a channel region CH defined in the channel layer 12. Further, the channel layer 12 is formed with diffusion regions 12A and 12B of the n-type at respective lateral sides of the gate electrode 13A, such that the diffusion regions 12A and 12B reach the GaAs substrate 11. Further, ohmic electrodes 13B and 13C are formed on the diffusion regions 12A and 12B respectively, and a passivation film 14 is provided on the channel layer 12 so as to cover the gate electrode 13A and the ohmic electrodes 13B and 13C.
In the enhancement-mode MESFET 10 of FIG. 1, it is necessary to increase the threshold voltage V.sub.th in order to reduce the leakage current in the turn-off state, wherein the threshold voltage V.sub.th is represented, in the injection type MESFET of FIG. 1, as EQU V.sub.th =V.sub.bi -qN.sub.d a.sup.2 /2.epsilon.,
wherein N.sub.d and a represent respectively the impurity concentration level and the thickness of the channel layer 12.
From the equation above, it is understood the impurity concentration level N.sub.d or the thickness a of the channel layer 12 has to be reduced when to increase the magnitude of the threshold voltage V.sub.th.
On the other hand, the characteristic curve of FIG. 2 indicates that the drain current I.sub.ds is reduced also when the impurity concentration level N.sub.d or the thickness a of the channel layer 12 is reduced. It should be noted that FIG. 2 represents the relationship between the drain current I.sub.ds and the gate voltage V.sub.gs. In other words, the relationship of FIG. 2 indicates that the maximum current density in the turn-on state of the MESFET 10 is reduced inevitably when the impurity concentration level N.sub.d in the channel layer 12 is reduced or the thickness a of the channel layer 12 is reduced for suppressing the turn-off state leakage current.
On the other hand, it has been known that the threshold voltage V.sub.th of a compound semiconductor device such as a MESFET is affected by the orientation of the gate electrode. Reference should be made, for example, to the Japanese Laid-Open Patent Publication 64-000770 or to the Japanese Laid-Open Patent Publication 57-135681. In relation to such a shift of the threshold voltage V.sub.th, caused by the setting of the gate electrode orientation on the compound semiconductor substrate, there is a stress analysis presented by Onodera (Onodera, T. et al., IEEE ED vol. 36, no. 9, pp. 1580-1590), concluding that such a change of the threshold voltage V.sub.th is caused as a result of the piezoelectric charges induced in the channel layer 12 in correspondence to the part right underneath the gate electrode 13A as represented in FIG. 3.
FIG. 4 represents the definition of the crystal orientation used in the present invention.
Referring to FIG. 4, an etch pit is formed on a (100)-oriented surface of a GaAs crystal by a wet etching process, wherein it can be seen that the crystal orientation [011] and the crystal orientation [011] are defined on the (100) surface based on the orientation of the ordinary mesa structure and the inverse mesa structure formed as a result of the wet etching process.
FIG. 5 shows the relationship between the gate length L.sub.g and the threshold voltage V.sub.th for the case in which the gate electrode 13A is formed in the [011] direction and also for the case in which the gate electrode 13A is formed in the [011] direction. The result of FIG. 5 assumes that the GaAs substrate 11 has a (100) principal surface.
Referring to FIG. 5, it can be seen that the threshold voltage V.sub.th decreases sharply with the gate length L.sub.g when the gate electrode 13A is formed in the [011] orientation. In this case, the threshold voltage V.sub.th drops conspicuously when the gate length L.sub.g has been reduced below 5 .mu.m. Thereby, the operational mode of the MESFET changes to the depletion mode. On the other hand, in the case the gate electrode 13A is formed in the [011] orientation, it can be seen that the threshold voltage V.sub.th remains more or less constant even in such a case in which the gate length L.sub.g is reduced below 5 .mu.m.
The result of FIG. 5 indicates that the MESFET 10 continues to operate in the enhancement-mode even in the case the gate length L.sub.g is reduced below 5 .mu.m, as long as the gate electrode 13A is formed in the [011] orientation.
On the other hand, the characteristic curve of FIG. 6 indicates that the drain current I.sub.ds is reduced, when the gate electrode 13A is formed in the [011] orientation. Apparently, this is due to the effect of the piezoelectric charges induced in the channel layer 12 in correspondence to the channel region CH right underneath the gate electrode 13A. It should be noted that FIG. 6 is a diagram similar to FIG. 2 and shows the relationship between the drain current I.sub.ds and the gate voltage V.sub.gs.
Further, in view of the fact that the gate turn-on voltage has a constant value of about 0.8 V in the construction of FIG. 1, in which the gate electrode 13A makes a direct Schottky contact with the channel layer 12, it has been difficult to construct an enhancement-mode MESFET having a threshold voltage V.sub.th exceeding 0.3 V, even if the gate electrode is formed with the [011] orientation. It should be noted that the foregoing constant gate turn-on voltage of about 0.8 V is determined by the Schottky barrier height formed between the gate electrode 13A and the channel layer 12.
In such a MESFET 10 having the characteristic of FIG. 6, it should be noted that the drain current I.sub.ds starts to decrease when the gate voltage V.sub.gs is applied with a magnitude exceeding the limit represented in FIG. 6 by a broken line. In such a case, there merely occurs an increase in the gate leakage current. Thus, in the MESFET 10 of FIG. 1, it is not appropriate to increase the gate voltage V.sub.gs beyond the foregoing limit. No further increase of the drain current I.sub.ds is expected even in the case the gate electrode 13A is formed with the [011] orientation.
Meanwhile, there is proposed a so-called HFET (heterostructure FET) in which the channel layer 12 of the MESFET 10 of FIG. 1 is covered by a high-resistance film of a compound semiconductor material having an increased bandgap. In an HFET, the gate electrode 13A and the source and drain electrodes 13A, 13B are formed on such a high-resistance compound semiconductor layer. Because of the existence of the high-resistance compound semiconductor layer between the gate electrode 13A and the channel layer 12, the HFET can successfully minimize the gate leakage current.
In the case of such an HFET, however, it was not obvious at all whether or not the piezoelectric charges are induced in the channel layer 12 in correspondence to the gate electrode 13A. The existence of the foregoing high-resistance layer between the channel layer 12 and the gate electrode 13A may change the stress field in the channel layer 12 drastically. Further, it is not obvious whether or not the optimization in the orientation of the gate electrode explained before with reference to the MESFET 10 of FIG. 1 is applicable to such an HFET. There has been no investigation about the optimization of the gate electrode orientation in an HFET.